1. Field of Invention
This present invention relates to a method and apparatus for creating fail-safe electrical components that employ dynamic logic circuitry to switch large power loads or to otherwise control circuits.
2. Description of Related Art
A thermal ink jet print head selectively ejects droplets of ink from a plurality of drop ejectors. The ejectors are operated in accordance with digital instructions to create a desired image on an image receiving member. The print head may move back and forth relative to the image receiving member to print the image in swaths or the print head may extend across the entire width of an image receiving member, to print the image without any scanning motion.
The ejectors typically comprise capillary channels, or other ink passageways, which are connected to one or more common ink supply manifolds. Ink is retained within each channel until, in response to an appropriate digital signal, the ink in the channel is rapidly heated and vaporized by a heating element disposed on a surface within a channel. This rapid vaporization of the ink adjacent the channel creates a bubble which causes a quantity of ink to be ejected through an opening associated with the channel to the print sheet. One patent showing the general configuration of a typical ink jet print head is U.S. Pat. No. 4,774,530, incorporated herein by reference in its entirety.
Within a device, such as a thermal ink jet print head, where control circuitry is used to control heating elements, an important design concern is the difference in voltage, and thus power, between the digital logic circuits used to fire the ejectors and the power circuits used to heat the ink or other fluids. In a typical thermal ink jet print head, for example, the digital logic signals which are used to activate particular ejectors at particular times to print an image typically operate at about 5 volts and the trend is to move to 3.3 V addressing logic. In particular, these relatively low voltage logic addressing circuits are used to switch drive transistors that turn on heating elements. In contrast, the heating elements typically require voltages in the range of 30 to 50 volts in order to provide the desired phase transformation of the liquid ink adjacent the heating element. In the case where it is desired to use lower voltages to operate the heating elements, more current is required, since joule heating is being employed.
Thermal ink jet print heads typically use integrated circuits which have large arrays of power transistors and associated heating elements, where only a subset of power transistors are to be switched on simultaneously. Typically, the heater element array is sequentially fired because the current draw per element is very large and activating all channels together could lead to rapid failure of the chip from over heating. Additionally, the firing order of the heating elements is frequently a ripple fire pattern and the shape of the heating pulses applied to each heater element is often complex and may be a function of the temperature of the print head. Finally, the increased resolution of inkjet print heads means that the amount of logic required to address at high resolution of inkjet print heads means that the amount of logic required to address at high resolution is increased. Accordingly, the logic circuits used to selectively address the power transistors have become increasingly complicated. To reduce the cost of this addressing logic and to reduce the area consumed by the addressing logic, dynamic, rather than static, logic circuits are used. Dynamic circuit elements retain information by storing charge. However, the charge is always leaking away from the dynamic circuit element storage nodes. The hold time of a dynamic circuit element is defined as the maximum amount of time before there is sufficient loss of stored charge such that the logic state of the circuitry becomes undefined. In many cases, the loss of stored charge is different for logic gates in the xe2x80x9c1xe2x80x9d state versus the xe2x80x9c0xe2x80x9d state so the output of the circuit is truly undefined. This may also be described as a xe2x80x9closs of state.xe2x80x9d
To prevent the loss of state, most systems require that the dynamic circuit elements must be refreshed in a time period that is less than the hold time of the dynamic circuit elements. If for some reason, such as a loss of connection to power, or time-dependent logic failures, the refresh event does not occur before the dynamic circuit elements lose state, then faulty circuit operation will occur.
In integrated circuits, such as thermal ink jet chips, which have large arrays of power transistors, where only a subset of power transistors are to be enabled simultaneously, the loss of state can cause a high current condition which can melt the interconnections between the chip and the power supply, if not the chip itself. A fuse in the system will not react as fast as the chip, and at a minimum the chip will be destroyed. In the case where a fuse is blown by excessive current flow, it is still necessary to replace the fuse to regain proper operation of the circuit. Thus, there is a need in thermal ink jet print heads to provide protection for this circuitry. It would be most desirable if the protection circuit was truly fail-safe i.e., such that the circuit and the component are still fully usable after the event.
This invention provides systems and methods that reduce the likelihood that a catastrophic consequence of a dynamic circuit losing state will occur.
This invention separately provides a dynamic fail safe circuit that reduces the likelihood that a catastrophic consequence will occur upon one or more dynamic circuit elements losing state.
This invention separately provides methods for determining a safety factor hold time for a dynamic fail-safe circuit.
This invention separately provides a dynamic fail-safe circuit that is locatable in close proximity to the dynamic circuit elements to be protected against consequences from losses of state.
This invention further provides a dynamic fail safe circuit that, by being located in close proximity to the dynamic circuit elements to be protected, will experience substantially the same process variations as the protected dynamic circuit elements.
In various exemplary embodiments, the systems and methods according to this invention protect dynamic circuit elements against the catastrophic effects of loss of state by providing a dynamic fail-safe circuit. This dynamic fail-safe circuit is refreshed at the same clock rate as the protected dynamic circuit elements. However, this dynamic fail-safe circuit has a hold time that is less than the hold time of the protected dynamic circuit elements, but more than the nominal refresh time. Thus, if the refresh signal is disrupted sufficiently that the protected dynamic circuit elements lose state, the dynamic fail-safe circuit will have previously exceeded its hold time, such that the dynamic fail-safe circuit is placed into a protection mode that protects the protected dynamic circuit elements from experiencing one or more catastrophic effects that would otherwise be experienced after the protected dynamic circuit elements lose state.
In various exemplary embodiments, the dynamic fail-safe circuit includes a dynamic latch. Under normal operation, the dynamic latch is maintained by the refresh signal in a first state that allows the integrated circuit containing the protected dynamic circuit elements to operate normally. When the dynamic latch is not refreshed within its fail-safe hold time, the dynamic latch reverts to a second state that protects the protected dynamic circuit elements.
In various exemplary embodiments, the dynamic fail-safe circuit also includes a number of AND gates. Each AND gate has an input connected to the dynamic latch, either directly or indirectly. The other input to the AND gate is connected to the dynamic logic circuit. The outputs of the AND gates are connected to a drive transistor array.
In the first state, the output of the dynamic latch is such that, directly or indirectly, a high logic signal is placed on one of the inputs to the AND gates. Thus, the AND gates pass the dynamic logic signal to the drive transistor array. In contrast, in the second state, the output of the dynamic latch is such that a low logic signal is placed on one of the inputs to the AND gates. Thus, the AND gates do not pass the dynamic logic signal to the drive transistors, thereby reducing the chances of a catastrophic consequence.
The hold time of the dynamic latch is selected so that, within a selected safety factor, state, the hold time of the dynamic latch will cause the dynamic latch to shift from the first state to the second state before the dynamic circuit elements lose state.
In various exemplary embodiments, the dynamic latch is formed on the same integrated circuit chip as the protected dynamic circuit elements. Thus, the dynamic latch experiences the same process variations as the protected dynamic circuit elements. These process variations can cause the hold times of the dynamic latch and the protected dynamic circuit elements to vary from the nominal design hold times. Because the dynamic latch and the protected dynamic circuit elements experience substantially the same variations, their hold times will vary in substantially the same way, substantially maintaining the relative values of the hold times.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the attached drawing, which disclose an exemplary embodiment of the invention.